1. Field of the Invention
This invention relates to semiconductor devices and more particularly to circuits designed to protect such devices from damage due to undesirable voltage conditions which can cause catastrophic damage to circuit elements, commonly referee to as electrostatic discharge (ESD) protection and overvoltage protection circuits and more particularly to on-chip ESD protection for semiconductor chips with mixed voltage interface applications and internal multiple power bus architecture.
2. Description of the Prior Art
The shrinking of MOSFET dimensions used in advanced integrated circuit technology for constructing a high circuit density and achieving performance objectives has required reduced power-supply voltages. With increased interest in portability, reduced power consumption in CMOS circuits is an important issue. Because power consumption is a function of CV.sup.2 f, the focus has been on reducing both capacitance, C, and power supply voltage, V, as the transition frequency increases. As a result, dielectric thickness continues to be scaled with the power-supply voltage. Power-supply reduction continues to be the trend for future low-voltage CMOS device scaling in advanced semiconductors.
The effect of MOSFET scaling on ESD protection has manifested itself in three ways: the shrinking of ESD structures and I/O circuitry, mixed-voltage interface environments, and noise isolation vs. ESD tradeoffs. On the first issue, reducing the area for both ESD structures and I/O circuitry makes structures more vulnerable; on the second, dual-voltage chips and mixing chip types forces new ESD structures to satisfy I/O needs; on the third issue, lower power-supply voltages are driving new bus architectures to isolate peripheral noise from internal core logic introducing new ESD concerns.